1) Field of the Invention
The present invention relates to a serial/parallel converter circuit with an uncertainty removing function suitably used in a communications system where a cable transmission line coexists with a radio transmission line or a communications system where plural cable transmission lines are networked.
2) Description of the Related Art
It has been often been arranged that communications between plural cable sections are relayed, for example, via a radio communication section. In the radio communication section, information from the cable transmission path is subjected to a signal conversion based on a predetermined modulation/demodulation system to transmit and receive.
In the radio transmission, the number of the transmission paths is dependent on the modulation/demodulation system used. The 16QAM (quadrature amplitude modulation) system, for example, allows communications via only four transmission paths.
In the above communications system, signals from 8 cable transmission paths, for example, are subjected to a parallel/serial conversion to multiplex, thus transmitting via 4 transmission paths across the radio communication section.
On the receiving side, the signals from the 4 transmission paths are subjected to a serial/parallel conversion to separate them so that the demultiplexed signals can be again transmitted through 8 cable transmission paths.
Thus the communications between the cable communication section and the radio communication section can be performed by using a serial/parallel converter circuit or a parallel/serial converter circuit.
In the 8 cable transmission paths as described above, when the radio communication section is a relay section employing a 16QAM modulation/demodulation system, 4 serial/parallel converter circuits, each which converts two parallel data into one serial datum, are arranged at the boundary portion where signals from the cable communication section are transmitted to the radio communication section, while 4 serial/parallel converter circuits, each which converts one serial datum into two parallel data, are arranged at the boundary portion where signals from the radio communication section are transmitted to the cable communication section.
A prior art serial/parallel converter circuit divides serially chained clocks by 2 to form clock chains in parallel, thus converting serial data into parallel data.
However, as described above, when a serial signal once converted by the parallel/serial converter circuit is converted again into parallel signals, the prior art serial/parallel converter circuit may cause two kinds of bit arrangements for parallel data because the starting point in the serial data is unclear at the clock frequency dividing timing for a parallel conversion.
For that reason, transmitting signals in the radio section may cause a difference in data arrangement (an uncertainty of a data arrangement) between data on the transmitting side and data on the receiving side.
In order to judge whether the data arrangement is correct, it may be considered to use a frame synchronizing method where signal bits are rearranged when a frame is out of synchronization in a fixed period of time or a data disarrangement occurs. However, there is a disadvantage in that this method takes much time to rearrange signal bits and cannot cope with an erroneous synchronization due to poor line quality, thus making suitable communications difficult.